4. For the hexadecimal main memory address BBBBBB, show the following information, in hexadecimal format:

(a). Tag, Line and Word values for a direct-mapped cache, using the format 8 bits for Tag, 14 bits for Line and 2 bits for Word.

(b). Tag and Word values for an associative cache, using the format 22 bits for Tag and 2 bits for Word.

(c). Tag, Set and Word values for a two-way set associative cache, using the format 9 bits for Tag, 13 bits for Lines and 2 bits for Word.

(d). How many Word(s) is(are) transferred each time between cache memory and main memory?

(e). How many Word(s) is(are) transferred each time between cache memory and CPU?