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4. Given the following latencies for the blocks in our datapath, what is the corresponding clock rate in the single-cycle design and the pipelined design,
4. Given the following latencies for the blocks in our datapath, what is the corresponding clock rate in the single-cycle design and the pipelined design, respectively? (4%) Instruction access: 2 ns Register read: 1 ns ALU operation: 2 ns Data memory access: 2 ns Register write-back: 1 ns
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