4. It is often needed to exchange the contents of two registers. It takes three instructions to accomplish this in MIPS. It might be useful to add a new instruction to the MIPS ISA that takes two registers and exchanges their contents. Suppose that the CPI is the same across all instruction types, and moreover is unaffected by the new instruction, but that the clock cycle time increases by 5%. Suppose that the n this newin truction reduces the total instruction count by 10%. Is it beneficial to implement enhancement? What is the overall speedup factor obtained? addition of this