4. Keeping the lowest stage (buffers closest to the sinks) buffer sizes at nfet (k=1) and pfet (k=2), change the buffer sizes of the next higher stage to nfet (k=2) and pfet (k=4), and change the buffer sizes of the highest stage (root of the tree) to nfet (k=4) and pfet (k=8) . Then using Elmore Delay analysis, calculate the individual stage delays. Also find the total delay from the root to a sink.

5. Find the power dissipation for the entire clock tree, as well as the stage wise power dissipations [For question 4 above]