4. Tasks 1. You are part of an intergalactic expedition that has arrived to a remote planet inhabited by creatures (lovely creatures); whose two hands have only 2 fingers each. It is soon discovered that their science and technology are not quite as advanced as they are on earth. It is also discovered that they use Tetral (a base-4 number system) for all their calculations. These beings would be greatly benefited if they had a rudimentary calculator to add two base-4 numbers and show the result in a couple of 7-segment displays. You are part of the expedition's elite engineering team and are asked to design and implement such calculator. Figure 1 shows the block diagram of what is required. 7 Tetral to 7-seg DEC Hex3 7 Tetral to 7-seg DEC Hex2 SW3 7 Tetral to 7-seg DEC A B SW2 Tetral adder Hex1 SWI SWO A+B 7 Tetral to 7-seg DEC Figure 1 Two-digit Tetral calculator (block diagram of top level schematic). a. Propose a binary representation for each of the four digits of the alien numeric system. (Each digit can be represented with two bits) (Pre-laboratory work) b. Build a truth table representing the addition of two Tetral numbers. Obtain the Boolean equations for each one of the output bits and simplify them, if possible. (Pre-laboratory work) c. Create a new project in Quartus II and add a schematic diagram for your Tetral adder. (30 minutes) d. Simulate your Tetral adder using Qsim and create the corresponding symbol. (20 minutes) e. Design a Tetral to 7-segments decoder. This component should convert the binary representation of one Tetral digit (two bits) into seven outputs controlling the segments of a display. Note that segments are turned ON with a 'O. (Pre-laboratory work) f. Create a new schematic diagram for your Tetral to 7-segments decoder using Quartus II. Use buses and make sure the signal controlling segment DO is connected to the output's least significant bit (the output with index 0). (30 minutes) g. Simulate your Tetral to 7-segments decoder using Qsim and create the corresponding symbol. (20 minutes) h. Use instances of your components in a top level schematic similar to Figure 1, generate the configuration file and test your calculator using the FPGA board. (20 minutes)