4. Virtual memory with TLB (translation look-aside buffer) (a) [5%] What is the purpose of the page table? (b) [590] When accessing the TLB is a miss, is it guaranteed that the processor cannot find the data in main memory? Why'? (c) [5%] Is it possible that TLB hits while virtual memory misses? Why? (d) [5%] Assume this is a cache. Is it possible that the TLB hits while the cache misses? Why