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4 - way set - associative L 1 D cache ( with 5 1 2 lines of 1 2 8 bytes each ) . The

4-way set-associative L1D cache (with 512 lines of 128 bytes each).
The cache has the following outputs:
Tag - shows the tag of the most recent line,
Set - shows the set of the most recent line,
Offset - shows the offset of the most recent line, and
Hit - shows a 1 if you get a cache hit or a 0 if you get a cache miss.
To test the cache, you clear it (you can assume it is completely empty before your test starts), and you program the processor to request the following addresses from RAM one after the other:
1)0x87654320
2)0x87654364
3)0x87654388
4)0x87658388
5)0x876583DC
If your cache is working properly, what are the expected output of Tag, Set, Offset, and Hit after each of the requests above (give your answers in hex).
Write your answer in a table as follows:
Address | Tag | Set | Offset | Hit
0x87654320|...|...|......|...
0x87654364|...|...|......|...
(and so on...)

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