4.26 This exercise is intended to help you understand the cost/complexity/ performance trade-offs of forwarding in a pipelined processor. Problems in this exercise refer to pipelined datapaths from Figure 4.53. These problems assume that, of all the instructions executed in a processor, the following fraction of these instructions has a particular type of RAW data dependence. The type of RAW data dependence is identified by the stage that produces the result (EX or MEM) and the next instruction that consumes the result (Ist instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register write is done in the first half of the clock cycle and that register reads are done in the second half of the cycle, so "EX to 3rd" and MEM to 3rd dependences are not counted because they cannot result in data hazards. We also assume that branches are resolved in the EX stage (as opposed to the ID stage), and that the CPI of the processor is 1 if there are no data hazards. MEM to 1" 1 Only Only Only 5% 20% 5% Assume the following latencies for individual pipeline stages. For the Ex stage, latencies are given separately for a processor without forwarding and for a processor with different kinds of forwarding. EX to EX to 2nd MEM to 2 Only 10% EX to 1" and EX to 2nd 10% ID EX (no FW) 110 ps EX (full FW) 130 ps IF 120ps EX (FW from EX/ MEM only) 120 ps EX (FW from MEM/ WB only) 120 ps MEM WB 100ps 120 ps 100 ps 4.26.1 [5] For each RAW dependency listed above, give a sequence of at least three assembly statements that exhibits that dependency. 4.26.2 [5] For each RAW dependency above, how many NOPs would need to be inserted to allow your code from 4.26.1 to run correctly on a pipeline with no forwarding or hazard detection? Show where the NOPs could be inserted. 4.26 This exercise is intended to help you understand the cost/complexity/ performance trade-offs of forwarding in a pipelined processor. Problems in this exercise refer to pipelined datapaths from Figure 4.53. These problems assume that, of all the instructions executed in a processor, the following fraction of these instructions has a particular type of RAW data dependence. The type of RAW data dependence is identified by the stage that produces the result (EX or MEM) and the next instruction that consumes the result (Ist instruction that follows the one that produces the result, 2nd instruction that follows, or both). We assume that the register write is done in the first half of the clock cycle and that register reads are done in the second half of the cycle, so "EX to 3rd" and MEM to 3rd dependences are not counted because they cannot result in data hazards. We also assume that branches are resolved in the EX stage (as opposed to the ID stage), and that the CPI of the processor is 1 if there are no data hazards. MEM to 1" 1 Only Only Only 5% 20% 5% Assume the following latencies for individual pipeline stages. For the Ex stage, latencies are given separately for a processor without forwarding and for a processor with different kinds of forwarding. EX to EX to 2nd MEM to 2 Only 10% EX to 1" and EX to 2nd 10% ID EX (no FW) 110 ps EX (full FW) 130 ps IF 120ps EX (FW from EX/ MEM only) 120 ps EX (FW from MEM/ WB only) 120 ps MEM WB 100ps 120 ps 100 ps 4.26.1 [5] For each RAW dependency listed above, give a sequence of at least three assembly statements that exhibits that dependency. 4.26.2 [5] For each RAW dependency above, how many NOPs would need to be inserted to allow your code from 4.26.1 to run correctly on a pipeline with no forwarding or hazard detection? Show where the NOPs could be inserted
