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4.33 Using the information in Tables 4-2 and 4-3 for the 74HC20 and the 74HC148 operating at 2.0 V, determine the maximum propagation delay from

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4.33 Using the information in Tables 4-2 and 4-3 for the 74HC20 and the 74HC148 operating at 2.0 V, determine the maximum propagation delay from any input to any output in a 32-to-5 priority encoder similar to Figure 7-13. A 74HC148 has active-low inputs and outputs and replaces each cascadable priority encoder," and you will also need to pick appropriate parts for the OR functions. Note that for this exercise you don't need to understand how the circuit works; you just need to find and analyze all of the delay paths. Hint: You don't have to compute the delay on every possible path, even after grouping the input and output signals. You should be able to "eyeball" the circuit structure to recognize only a handful of paths that may be able to produce the worst-case delav Cascadable priority encoders Figure 7-13 G2 G3A1 G Four 8-input encoders casca handle 32 roues REQ31 REQ30 REQ29 REQ28 REQ27 REQ26 REQ25 REQ24 G3GS G 1 G2A2 G2A1 G2A0 4-10-2 encoder REQ23- REQ22 REQ21 REQ20 REQ19 REQ18 REQ17 - REQ16 - G2GS G2EO G1A2 G1A1 G1A0 REQ15 REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQB G1GS G1EO AAAAA GOA2 GOA1 GOAO REQ7 REQ6 REQS REQ4 REQ3 REQ2 REQ1 REQO GOGS Part 10.0 7 2.6 G1 GS 4.2 Circuit Timing 163 ble 4-3 Propagation delay in nanoseconds of selected CMOS MSI parts. 74AC @ 5.0V 74HC e 2.0V 74HC 4.5V Min. Max. Typ. Maximum Typ. Maximum 25C 25C 85C Function From Top 25C 25C 85C 3-10-8 binary any select output 2.8 150 decoder 225 18 36 45 G2A. G2B output 9.1 155 195 18 31 39 output 2.8 "139 dual any select output 2.8 2-to-4 binary decoder enable output 2.8 9.5 39 175 220 11 148 8-to-3 11-17 AO-A2 69 180 225 23 36 priority encoder 10-17 EO 10-17 75 190 240 25 Ei AO- A2 7 8 195 245 26 EIGS 57 145 180 19 EI EO 66 165 205 22 "151 8-to-1 any select Yol 4.7 16. 5 94 250 312 30 multiplexer any select Y 5.1 17.8 94 250 312 30 any data Y 3.5 12. 3 74 195 244 23 any data Y 3.8 13.5 74 195 244 23 enable Y 3.1 11.1 49 127 159 15 enable Y 3.5 12. 3 49 127 159 15 25 "1572-10-4 select output 3.8 13.2 145 180 12 multiplexer any data output 2.2 7.7 125 155 10 25 31 135 170 output 11 27 enable 34 200 250 EVEN 17 40 50 -input parity any input circuit ODD 200 250 17 any input 40 50 *283 230 4-bit adder 290 4 6 19 58 210 4.7 265 18 42 any Ai, Biany Si 53 4.5 04 16.0 195 any input 245 16 3949 130 275 344 26 082 8-bit comp any input output LAM any Si 4.2 Clicuit my TO Table 4-2 Propagation delay in nanoseconds of selected CMOS SSI parts. 74AC @ 5.0V 76HC @ 2.0v 74HC @ 4.5V Minimum Maximum Typ. Waximun Typ. Maximum 25C 25C 85C 25C Part Number '00 02 204 08 '10 pHL 1.9 3.0 1.7 1.0 1.0 plafphl 6.6 6.6 10.4 10.4 5.9 5.9 8.5 7.5 8.0 6.5 Function 2-input NAND 2-input NOR Inverter 2-input AND 3-input NAND 3-input AND 4-input NAND 4-input AND 3-input NOR 8-input NAND 2-input OR 2-input XOR pH 1.9 3.0 1.7 1.0 1.0 1.0 1.5 1.5 1.5 1.0 1.5 1.0 90 90 95 100 95 100 110 110 90 130 100 100 115 115 120 125 120 125 140 140 115 165 125 125 45 45 50 35 35 45 44 35 41 50 40 25C 85C Apd Apa 18 23 18 23 19 24 20 25 19 24 20 25 22 28 22 28 18 23 26 33 20 25 20 25 9 9 10 10 10 14 14 10 15 10 12 20 21 27 30 "32 '86 1.5 1.5 1.5 1.0 10 1.0 8.0 6.5 8.5 9.5 10.0 9.0 7.0 7.0 8.5 9.5 9.0 9.5 matrical outnut driving capability, so the delays 4.33 Using the information in Tables 4-2 and 4-3 for the 74HC20 and the 74HC148 operating at 2.0 V, determine the maximum propagation delay from any input to any output in a 32-to-5 priority encoder similar to Figure 7-13. A 74HC148 has active-low inputs and outputs and replaces each cascadable priority encoder," and you will also need to pick appropriate parts for the OR functions. Note that for this exercise you don't need to understand how the circuit works; you just need to find and analyze all of the delay paths. Hint: You don't have to compute the delay on every possible path, even after grouping the input and output signals. You should be able to "eyeball" the circuit structure to recognize only a handful of paths that may be able to produce the worst-case delav Cascadable priority encoders Figure 7-13 G2 G3A1 G Four 8-input encoders casca handle 32 roues REQ31 REQ30 REQ29 REQ28 REQ27 REQ26 REQ25 REQ24 G3GS G 1 G2A2 G2A1 G2A0 4-10-2 encoder REQ23- REQ22 REQ21 REQ20 REQ19 REQ18 REQ17 - REQ16 - G2GS G2EO G1A2 G1A1 G1A0 REQ15 REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQB G1GS G1EO AAAAA GOA2 GOA1 GOAO REQ7 REQ6 REQS REQ4 REQ3 REQ2 REQ1 REQO GOGS Part 10.0 7 2.6 G1 GS 4.2 Circuit Timing 163 ble 4-3 Propagation delay in nanoseconds of selected CMOS MSI parts. 74AC @ 5.0V 74HC e 2.0V 74HC 4.5V Min. Max. Typ. Maximum Typ. Maximum 25C 25C 85C Function From Top 25C 25C 85C 3-10-8 binary any select output 2.8 150 decoder 225 18 36 45 G2A. G2B output 9.1 155 195 18 31 39 output 2.8 "139 dual any select output 2.8 2-to-4 binary decoder enable output 2.8 9.5 39 175 220 11 148 8-to-3 11-17 AO-A2 69 180 225 23 36 priority encoder 10-17 EO 10-17 75 190 240 25 Ei AO- A2 7 8 195 245 26 EIGS 57 145 180 19 EI EO 66 165 205 22 "151 8-to-1 any select Yol 4.7 16. 5 94 250 312 30 multiplexer any select Y 5.1 17.8 94 250 312 30 any data Y 3.5 12. 3 74 195 244 23 any data Y 3.8 13.5 74 195 244 23 enable Y 3.1 11.1 49 127 159 15 enable Y 3.5 12. 3 49 127 159 15 25 "1572-10-4 select output 3.8 13.2 145 180 12 multiplexer any data output 2.2 7.7 125 155 10 25 31 135 170 output 11 27 enable 34 200 250 EVEN 17 40 50 -input parity any input circuit ODD 200 250 17 any input 40 50 *283 230 4-bit adder 290 4 6 19 58 210 4.7 265 18 42 any Ai, Biany Si 53 4.5 04 16.0 195 any input 245 16 3949 130 275 344 26 082 8-bit comp any input output LAM any Si 4.2 Clicuit my TO Table 4-2 Propagation delay in nanoseconds of selected CMOS SSI parts. 74AC @ 5.0V 76HC @ 2.0v 74HC @ 4.5V Minimum Maximum Typ. Waximun Typ. Maximum 25C 25C 85C 25C Part Number '00 02 204 08 '10 pHL 1.9 3.0 1.7 1.0 1.0 plafphl 6.6 6.6 10.4 10.4 5.9 5.9 8.5 7.5 8.0 6.5 Function 2-input NAND 2-input NOR Inverter 2-input AND 3-input NAND 3-input AND 4-input NAND 4-input AND 3-input NOR 8-input NAND 2-input OR 2-input XOR pH 1.9 3.0 1.7 1.0 1.0 1.0 1.5 1.5 1.5 1.0 1.5 1.0 90 90 95 100 95 100 110 110 90 130 100 100 115 115 120 125 120 125 140 140 115 165 125 125 45 45 50 35 35 45 44 35 41 50 40 25C 85C Apd Apa 18 23 18 23 19 24 20 25 19 24 20 25 22 28 22 28 18 23 26 33 20 25 20 25 9 9 10 10 10 14 14 10 15 10 12 20 21 27 30 "32 '86 1.5 1.5 1.5 1.0 10 1.0 8.0 6.5 8.5 9.5 10.0 9.0 7.0 7.0 8.5 9.5 9.0 9.5 matrical outnut driving capability, so the delays

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