$(50$ Pts$)$ Design a VHDL model to implement the behavior of the function F $=$

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Draw a truth table for the function F$.$

Use a process and an if$/$then statement. Use std$\_$logic and std$\_$logic$\_$vector for your signals.

Declare the entity to match the block diagram below. Use the entity name HW$9\_$SU$24.$

Design a VHDL test bench to verify the function operation.

Your test bench should drive in each input code for the vector ABCD in the order they appear in the truth table $(0000,0001,0010,.....).$

Have your test bench change the input pattern every $100$ ns using wait for statement within your stimulus process.

Name your test bench file HW$9\_$TB

Submit a screenshot showing the simulation results and all the combinations of the vector ABCD.

Submit your VHDL your source and Test Bench files.