5. [0010/10/10/10/10] For each part of this exercise, the initial cache and memory state are assumed to initially have the contents shown in Figure 5.37. Each part of this exercise specifies a sequence of one or more CPU operations of the form Core 0 Core 1 Core3 Line number Cache state Address Data AC00 0010 ACOB 0008 AC10 0030 AC 18 0010 state Address Data state Address Data line ACCO 0010 AC28 0068_ AC10 0010 AC18 0018 AC20 20 ACO8 0008 AC10 0010 AC18 0010 ACOO 0010 AC08 0008 AC10 0010 AC18 0018 AC20 0020 AC28 0028 AC30 0030 Memory Figure 5.37 Multicore (point-to-point) multiprocessor Ccore#: R,

for reads an Ccore#: W,

for writes. For example, C3: R, AC 10 & CO: W, AC 18 CO: R, AC20 b. [10] CO: W, AC20 C3: W, AC20 C1: R, AC10 e. [10] CO: W, AC08 CO: W, AC30 C3: W, AC30 For each part of this exercise, the initial cache and memory state are assumed to initially have the contents shown in Figure 5.37. Each part of this exercise specifies a sequence of one or more CPU operations of the form Core 0 Core 1 Core3 Line number Cache state Address Data AC00 0010 ACOB 0008 AC10 0030 AC 18 0010 state Address Data state Address Data line ACCO 0010 AC28 0068_ AC10 0010 AC18 0018 AC20 20 ACO8 0008 AC10 0010 AC18 0010 ACOO 0010 AC08 0008 AC10 0010 AC18 0018 AC20 0020 AC28 0028 AC30 0030 Memory Figure 5.37 Multicore (point-to-point) multiprocessor Ccore#: R,

for reads an Ccore#: W,

for writes. For example, C3: R, AC 10 & CO: W, AC 18 CO: R, AC20 b. [10] CO: W, AC20 C3: W, AC20 C1: R, AC10 e. [10] CO: W, AC08 CO: W, AC30 C3: W, AC30