5. [11 points] Consider a 5-stage IF, ID, EX, MEM and WB pipeline as specified in Figure 4.46. The branch address is calculated in the Execution stage. Data forward is used. In the case of data hazard, we need to stall the execution (a) Draw the pipeline execution diagram for the first 13 clock cycles Make sure to indicate stalls and show data forwarding from a source stage to a destinatiorn stage. (b) Specify the control signals (1.e., F?rwa rdA, ForwardB) f?r each data forwa rded Use Figure 4.57 to analyze the control signals. addi $s0, $zero, 2 addi ?sl, $s0, 100 I2: I3: loop: l ?to, 0 ($sl) I4: I5: I6: 17: I8: I9: I10: lw $t1, 10 (St0) add ?t0, $tl, ?tl sw t0, 0 (?s1) add $sl, ?zero, $t0 addi $s0, $s0,1 bne $s0, $zero, loop add Sv0, L,$zero [Use the answer sheets] 5. [11 points] Consider a 5-stage IF, ID, EX, MEM and WB pipeline as specified in Figure 4.46. The branch address is calculated in the Execution stage. Data forward is used. In the case of data hazard, we need to stall the execution (a) Draw the pipeline execution diagram for the first 13 clock cycles Make sure to indicate stalls and show data forwarding from a source stage to a destinatiorn stage. (b) Specify the control signals (1.e., F?rwa rdA, ForwardB) f?r each data forwa rded Use Figure 4.57 to analyze the control signals. addi $s0, $zero, 2 addi ?sl, $s0, 100 I2: I3: loop: l ?to, 0 ($sl) I4: I5: I6: 17: I8: I9: I10: lw $t1, 10 (St0) add ?t0, $tl, ?tl sw t0, 0 (?s1) add $sl, ?zero, $t0 addi $s0, $s0,1 bne $s0, $zero, loop add Sv0, L,$zero [Use the answer sheets]