5. For a direct mapped cache design with 32-bit address, the following bits of the address are used for these fields: Offset from 0 to 3, Index from 4 to 7, and Tag from 8 to 31. Starting from power on, the byte-addressed cache references shown in the table are made. For such a scenario, complete the table. (15 points) Tag Binary 0...010000000000 0...000000000100 0. . .01 01000000 0...010000100000 o... 011110000000 0...000000000000 0.. . 00000001 0000 0...010100000000 Index Hit/Miss Replace