5. Using Verilog HDL, designra binary adder using three NOT-MAJORITY gates and two inverters as shown below. (Test benn and simulation are not required) MAJD 1 0 MAJ Sum a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 MAJ