5) VHDL Analysis: The following VHDL code describes a simple Finite State Machine Library ieee; ieee.std logie 1164. al1 Use ieee . numeric std . all ; Entity FSM is port( clock, A : in std logic; X, Y, Z: out std logic End Entity FSM Architecture rtl of FSM is Type state is s0, sl, s2, s3); signal NS, Ps states0; Begin SubSystem Block ( clock - '1' and not clock' stable ) Signal T: std logic vector (1 downto 0); begin PS