[50 pts] Sequence Detector FSM: Consider an FSM that has a 1-bit input A and a 1-bit output F (found). Design a Moore FSM that repeatedly detects the serial input: 11010. When that input is detected, the output F should assert for one clock cycle. So, A changes over time - it is a serial input, because a new bit appears on that signal each clock cycle. For example, the output assert after each of (5-bit) bolded sequences are detected in the following input stream (A): A: 001011010010110110100100001010110101101001000010111101110100010 Show all steps of the FSM design process ending up with a complete schematic. Use 1hot encoding and a minimum number of states