54 - Appendix B Review of Memory Hierarchy B.8 [5/5/5] We want to observe the following calculation d: - i+h; *li, 1:10:511) Arrays et, b. c. and d memory layout is displayed below (each has 512 4-byte-wide integer elements), The above calculation employs a for loup that runs through S12 iterations. Assume a 32 Kbyte 4-way set associative cache with a single cycle access time. The miss penalty is 100 CPU cycles/access, and so is the cost of a write-back. The cache is a wille-hack ni hils while-allocal i ruisses cuche (Figure 1.32). a. [5] How many cycles will an iteration take if all three loads and single Slure miss in the data cache! b. [5]If the cache line size is 16 bytes, what is the average number of Cycles an average ileration will take? (Hint: Spatial l alily!) c. [5]If the cache line size is 64 bytes, what is the average number of Cycles an average ilcrution will take? d. If the cache is direct-mapped and its size is reduced to 2048 bytes, what is the uverage number of cycles an average iteration will take? B.8 (5/5/5] We want to observe the following calculation di = 0; +b; *c. : (0:511) Arrays a, b, c, and d memory layout is displayed below (each has 512 4-byte-wide integer elements). The above calculation employs a for loop that runs through 512 iterations. Assume a 32 Kbyte 4-way set associative cache with a single cycle access time. The miss penalty is 100 CPU cycles/access, and so is the cost of a write-back. The cache is a write-back on hits write-allocate on misses cache (Figure B.32). a. [5] How many cycles will an iteration take if all three loads and single store miss in the data cache? b. 151If the cache line size is 16 bytes, what is the average number of cycles an average iteration will take? (Hint: Spatial locality!) C. [5] If the cache line size is 64 bytes, what is the average number of cycles an average iteration will take? d. If the cache is direct-mapped and its size is reduced to 2048 bytes, what is the average number of cycles an average iteration will take? 54 - Appendix B Review of Memory Hierarchy B.8 [5/5/5] We want to observe the following calculation d: - i+h; *li, 1:10:511) Arrays et, b. c. and d memory layout is displayed below (each has 512 4-byte-wide integer elements), The above calculation employs a for loup that runs through S12 iterations. Assume a 32 Kbyte 4-way set associative cache with a single cycle access time. The miss penalty is 100 CPU cycles/access, and so is the cost of a write-back. The cache is a wille-hack ni hils while-allocal i ruisses cuche (Figure 1.32). a. [5] How many cycles will an iteration take if all three loads and single Slure miss in the data cache! b. [5]If the cache line size is 16 bytes, what is the average number of Cycles an average ileration will take? (Hint: Spatial l alily!) c. [5]If the cache line size is 64 bytes, what is the average number of Cycles an average ilcrution will take? d. If the cache is direct-mapped and its size is reduced to 2048 bytes, what is the uverage number of cycles an average iteration will take? B.8 (5/5/5] We want to observe the following calculation di = 0; +b; *c. : (0:511) Arrays a, b, c, and d memory layout is displayed below (each has 512 4-byte-wide integer elements). The above calculation employs a for loop that runs through 512 iterations. Assume a 32 Kbyte 4-way set associative cache with a single cycle access time. The miss penalty is 100 CPU cycles/access, and so is the cost of a write-back. The cache is a write-back on hits write-allocate on misses cache (Figure B.32). a. [5] How many cycles will an iteration take if all three loads and single store miss in the data cache? b. 151If the cache line size is 16 bytes, what is the average number of cycles an average iteration will take? (Hint: Spatial locality!) C. [5] If the cache line size is 64 bytes, what is the average number of cycles an average iteration will take? d. If the cache is direct-mapped and its size is reduced to 2048 bytes, what is the average number of cycles an average iteration will take