5.6.1 Design a VHDL model to implement the behav- ior described by the 3-input minterm list shown in Fig. 5.11. Use a structural design approach and basic gates. You will need to create what- ever basic gates are needed for your design (e.g., INV1, AND2, OR4) and then instantiate them in your upper level architecture to create the desired functionality. The lower level gates can be implemented with concurrent signal assignments and logical operators (e.g., F