6. Consider the parallel port illustrated in the figure below. 68HC11 Demultiplexed Address Bus Ais - Ao Data Bus AD7 - AD. R/W E --- RSTATUS PSTATUS AD7 AD *** ADO .. Control Address RPORT A A Logic PDATA Decoding O 0 OS Qo . +5V STATUS HOD QD DI CLR PARALLEL PORT INTERFACE ... KEYBOARD (a) Find Boolean logic expressions to generate the active high signals PSTATUS and PDATA when the address bus contents are $A000 and SA001, respectively. Use the fewest lines possible. No addresses outside the range SA000-$A7FF should assert PSTATUS or PDATA 13 pts) (b) RSTATUS and RPORT are the control signals used by the HCI to read the status bit and the data register of the parallel port, respectively. Find the Boolean expressions for RSTATUS and RPORT, both to be active high for E clock cycle [3 pts] (c) In the diagram above, label the VALID and ACK (acknowledge) lines for the keyboard, connect them to the appropriate places where necessary, and complete all required connections for signals RSTATUS, RPORT and the D flip-flops (the status bit and those in the data register), Status bit to be set to 'l' in order to indicate that new data is available in data register. 3 pts] (d) In the timing diagram below, sketch waveforms for the signals VALID, ACK, RPORT and the state of the STATUS bit to make them consistent with what is shown on the O-Qo data lines of the port interface. Assume interlocked handshake as the control protocol. Draw arrows indicating which signal: (1) Causes the change in the data value in Q-Qo, and (2) Clears the status bit. All signals are binary (high/low), no need for scale values. [3 pts) E Q7-Qo SA7 $29 RPORT VALID ACK STATUS 6. Consider the parallel port illustrated in the figure below. 68HC11 Demultiplexed Address Bus Ais - Ao Data Bus AD7 - AD. R/W E --- RSTATUS PSTATUS AD7 AD *** ADO .. Control Address RPORT A A Logic PDATA Decoding O 0 OS Qo . +5V STATUS HOD QD DI CLR PARALLEL PORT INTERFACE ... KEYBOARD (a) Find Boolean logic expressions to generate the active high signals PSTATUS and PDATA when the address bus contents are $A000 and SA001, respectively. Use the fewest lines possible. No addresses outside the range SA000-$A7FF should assert PSTATUS or PDATA 13 pts) (b) RSTATUS and RPORT are the control signals used by the HCI to read the status bit and the data register of the parallel port, respectively. Find the Boolean expressions for RSTATUS and RPORT, both to be active high for E clock cycle [3 pts] (c) In the diagram above, label the VALID and ACK (acknowledge) lines for the keyboard, connect them to the appropriate places where necessary, and complete all required connections for signals RSTATUS, RPORT and the D flip-flops (the status bit and those in the data register), Status bit to be set to 'l' in order to indicate that new data is available in data register. 3 pts] (d) In the timing diagram below, sketch waveforms for the signals VALID, ACK, RPORT and the state of the STATUS bit to make them consistent with what is shown on the O-Qo data lines of the port interface. Assume interlocked handshake as the control protocol. Draw arrows indicating which signal: (1) Causes the change in the data value in Q-Qo, and (2) Clears the status bit. All signals are binary (high/low), no need for scale values. [3 pts) E Q7-Qo SA7 $29 RPORT VALID ACK STATUS