6. Design a synchronous sequential circuit that has an input w and an output z. The circuit acts as a sequence edge detector: z=1 when the input bit stream changes from 0 to 1 or from 1 to 0, otherwise z=0. a. Define the states and give the state diagram or FSM (either Moore machine or Mealy machine) [10 pts] b. Give the state transition table with the inputs to the JK flip flops and the output. [5pts] c. Draw the schematic of the circuit using the above specified components and logic gates. [5 pts]