(6 points) For the pipelined datapath of chapter 4 . There are five stages: IF, ID, ALU OP, MEM, and WB. Assume each stage actual latency is 200ps. 1. If the time taken by the AlU op stage is reduced by 25%, will it affect the speedup of the Pipeline? If yes, by how much? If no, why? yes2,5 2. If the time take by the ALU op stage is increased by 25%, will it affect the speedup of the Pipeline? If yes, by how much? If no, why