7. Suppose that you are designing a write buffer between a write-through L1 cache

and a write-back L2 cache. The L2 cache write data bus is 16-byte wide and can

perform a write to an independent cache address every 4 processor cycles.

a. What speedup could be expected in the steady state by using a merging write

buffer instead of a non-merging buffer when zeroing memory by the execution

of 64-bit stores if all other instructions could be issued in parallel with the

stores and the blocks are present in the L2 cache?

b. Consider the usage of critical word first and early restart on L2 cache misses.

Assume a 1 MB L2 cache with 64-byte blocks and a refill path that is 16-byte

wide, the time to receive the first 16-byte block from the memory controller is

100 cycles, each additional 16-byte block from main memory requires 25

cycles, and data can be bypassed directly into the read port of the L2 cache.

Ignore any cycles to transfer the miss request to the L2 cache and the

requested data to the L1 cache. How many cycles would it take to service an

L2 cache miss with and without critical word first and early restart?

c. According to b., do you think critical word first and early restart would be

more important for L1 caches or L2 caches, and what factors would contribute

to their relative importance?