88 [5/5/5] We want to observe the following calculation di-ai + bi * Ci, 1:0): Arrays a, b, c, and d memory layout is displayed below (each has 512 4-byte-wide integer elements). The above calculation employs a for loop that runs through 512 iterations. Assume a 32 Kbyte 4-way set associative cache with a single cycle access time. The miss penalty is 100 CPU cycles/access, and so is the cost of a write-back. The cache is a write-back on hits write-allocate on misses cache (Figure B.32) a. [5]How many cycles will an iteration take if all three loads and single store miss in the data cache? b. [5] If the cache line size is 16 bytes, what is the average number of cycles an average iteration will take? (Hint: Spatial locality!) Mem. address in bytes 0-2047 2048-4095 4096-6143 6144-8191 Contents Array a Array b Array c Array d Figure B.32 Arrays layout in memory. 88 [5/5/5] We want to observe the following calculation di-ai + bi * Ci, 1:0): Arrays a, b, c, and d memory layout is displayed below (each has 512 4-byte-wide integer elements). The above calculation employs a for loop that runs through 512 iterations. Assume a 32 Kbyte 4-way set associative cache with a single cycle access time. The miss penalty is 100 CPU cycles/access, and so is the cost of a write-back. The cache is a write-back on hits write-allocate on misses cache (Figure B.32) a. [5]How many cycles will an iteration take if all three loads and single store miss in the data cache? b. [5] If the cache line size is 16 bytes, what is the average number of cycles an average iteration will take? (Hint: Spatial locality!) Mem. address in bytes 0-2047 2048-4095 4096-6143 6144-8191 Contents Array a Array b Array c Array d Figure B.32 Arrays layout in memory