$9\mathrm{.}1$ Introduction to Verilog zyLabs

A zyLab lets the student design logic in a Verilog file or file hierarchy and test whether the design compiles and simulates to meet specifications. The simulator uses testbenches created by the zyLab's author to verify the design. In addition to the complete testbenches, a Verilog design template file is provided to ensure the correct signal I$/$O names and'types.

This introductory zyLab is a simple $2-$way multiplexer module mux$2,$ that implements $y=s^{\text{'}}a+sb.$ Download the template and testbench via the Download button $($as shown in the screen capture below, Step $1).$ The mux$2.$v file may be edited and simulated in a logic IDE $($Integrated Development Environment$)$ such as Quartus Prime or Vivado. Alternatively, modify mux$2.$v via a text editor if an IDE is not available. Sscreen capture of the buttons to download the template and upload and submit student work Then upload $($Step $2)$ the mux$2.$v file and click the Submit for grading button $($Step $3)$ to have the zyLab Verilog compiler and simulator validate the design and award points. If errors occur, revise the design and resubmit.

The zyLab simulator will print green check marks for tests that passed, but red $x$ marks for failed tests:

Zscreen capture of simulator output

Clicking on the Select signals to show arrow

rscreen capture of simulator output

followed by clicking Select all $..$

$2$screen capture of select signals to show menu, with a checkbox for each signal $...$ will display a graph of the simulated signals, which can be scrolled and zoomed:

waveforms for signals $a,b,s,$ and y