A 128K X 32 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. a) Assuming that the RAM cell array is square, what is the size of each decoder? b) Determine the row and column selection lines that are enabled when the input address is 0x39ABCD. c) Why is "squareness" a good assumption? A 128K X 32 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. a) Assuming that the RAM cell array is square, what is the size of each decoder? b) Determine the row and column selection lines that are enabled when the input address is 0x39ABCD. c) Why is "squareness" a good assumption