A 1-bit ALU selects and performs 4 operations based on the 2 select bits(S1,S0). The whole ALU consists of the 2 select bits, 2 input bits(A,B), and 1 output(F). A special input(CarryIn) and output(CarryOut) is also integrated into the ALU for specifically the addition function. The output F is dependent on the select bit because the select bit choose which operation it will perform.

URGENT make a Verilog program that satisfies this test bench for a 8-Bit ALU!!! Pictures swapped in order, The specific requirements for this includes designing and exhaustively testing a 1-bit ALU using dataflow. This is done in order to insure that the 8-bit ALU will work. Once the 1-bit ALU works, an 8-bit ALU needs to be designed using multiple instances of the 1-bit ALU. This 8-bit ALU is required to have 2 1-bit select bits(S1,S0) but with inputs(A,B) and output(F) being 8 bits wide. A 1-bit wide CarryIn and CarryOut bit will also be integrated into the 8-bit ALU. All this needs to be tested using the test bench provided to us on the class website.

(SI, SO} = 2 'b10, for (stimulus-0 stimulus