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A 4 - bit shift register, which shifts 1 bit to the right at every clock pulse, The D input is derived from Q 0

A 4- bit shift register, which shifts 1 bit to the right at every clock pulse, The D input is derived from Q0, Q2 and Q3 through two
2- input XOR gates as shown in figure. a) At what values should the shift register be initialized so that the pattern (1101) occurs
after the second clock pulse?
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