a) A 5-Stage pipeline is composed of the following stages Instruction Fetch (IF), Decode (DE), Execute (EX), Memory Access (ME) and Register Write-back (WB). Assume the pipeline does not have a branch prediction unit, does not have superscalar support and does not support out of order execution. Assume that all memory accesses are in the L1 cache and therefore they do not introduce any stalls (as we assumed in Lecture). Show a pipeline diagram that shows the execution of each stage for the assembly code below. Also specify why each pipeline Stall is introduced. (16 points) addq %rax, (%rbx) subq %rcx, %rax movq $0, %rdx movq $1, %rdx xorq %rsi, (%rbx) movq %rsi, %r10 movq %r10, %r11