a) Assume a cache hierarchy, where we have separate cache for instructions and data where the miss penalty for both is 100 cycles. The miss rate of the instruction cache is 4%; on the other hand, the miss rate for the data cache is 8%. If the processor has a CPI of 1.2 without any memory stalls. Assume the frequency of all loads and stores is 30% (combined). Calculate the effective CPI of the system, by accounting for the cache miss penalty. b) Consider a cache that has 4096 blocks, where each block contains 8 words. Assuming a 32-bit address, find the total number of tags bits and index bits for this for this cache when it is: i) direct mapped ii) 4-way set associative iii) 8-way set associative iv) fully-associative