A benchmark executed in a five-stage pipelined processor has the following characteristics: 41% ALU instructions 29% load instructions 84% of the loads are immediately followed by instructions that use the data being loaded 36% of these loads are followed by stores. Let us assume that the destination register for the load instruction is Ry. For the store instructions which have dependencies on the loads: 65% of the stores have the form: STR Ry, [Rx] ; M[Rx]