Question
A) Build a 4bit register (nibble) (3 points): You should implement one nibble (4 bits) using flipflops. The corresponding starter subcircuit (nibble) is prepared for
A) Build a 4bit register (nibble) (3 points): You should implement one nibble (4 bits) using flipflops. The corresponding starter subcircuit (nibble) is prepared for you with proper input /output ports. Fill it with proper circuitries. Your circuit should perform read and write operations in one clock cycle. In other words, if we want to write (Read_Write = 0, and En =1), the value of Data should be saved in the flipflops. Also, thisvalue should be appeared in the Nibble_Out within one clock cycle. Otherwise, if En =0, no write operation should be performed. In other words, the last value of Nibble should be presented on the Nibble_out. However, if Read_Write = 1 the value of the Nibble should be observed on the Nibble_Out no matter what the value of En is. You may add a clk source in the nibble circuit to check/test its functionality. Do not forget to remove it. Nibble should receive its clks signal from the higher module (16nibble RAM).
Build a 16nibble RAM (10 points): To do so, you should use the nibble that you synthesized in the previous part to make your 16nibble RAM. You require to fill out the starter subcircuit (RAM_16_Nibbles) with proper circuitries as it is mentioned below: Your circuit should perform read and write operations in one clock cycle. In other words, if we want to read (Read_Write =1), in the next Clk the value of the nibble that address bits indicates should be observed in the RAM_Out. Your RAM circuit should read a 4bit data from input and set it as the value of the nibble that is defined by the address bits. For example, if Data = 1000 and Address = 0011, then in the next Clk cycle the value of 4th nibble of the RAM should become 1000, and also this value should be displayed on the output. Note that each module should not have its own clock source. The circuit should have just one single Clk source that is located in RAM_16_Nibbles module. If the nibble module requires a clk signal to work properly, pass the clk signal from RAM_16_Nibbles to Nibble subcircuit as an input for Nibble subcircuit.
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