A byte addressable computer has a small data cache capably of holding eight 32 bit words. Each cache block consists ofd one 32-bit word. When a given program is executed, the processor reads data sequentially from the following hex addresses

200, 204, 208, 20C, 2F4, 2F0, 200, 204, 218, 21C, 24C, 2F4,

This pattern is repeated four times.

a) Assume that the cache is initially empty. Show the contents of the cache at the end of each pass through the loop if a direct mapped cache is used, and compute hit rate

b) Repeat part a) for a fully associative cache that uses LRU replacement algorithm

c) Repeat part a) for a four-way set associative cache with LRU replacement