(a) Compare the timing diagrams of the major steps of instruction execution of a normal processor and a pipelined processor. [6 marks] (b) Explain which of the following two pipelined processors would have the higher execution speed. Processor A uses 25 stages to implement an instruction, each stage taking 200ns. Processor B uses 100 stages to implement an instruction, each stage taking 100ns. [4 marks] (c) In which category would a pipelined processor belong when classified according to multiplicity of instruction and data streams? Illustrate the category using a diagram. [4 marks] (d) What are low order and high order interleaving memory addressing schemes? [6 marks]