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a ) Consider the following loop [ 2 ] [ 1 ] [ 1 ] [ CLO - 3 , C 4 Analysis, PLO -

a) Consider the following loop
[2]
[1][1]
[CLO-3, C4 Analysis, PLO-4 Investigation]
[2]
for i in range if~X[i]l=0
(256):
Is the above loop vectorizable? If not, then show where the problem lies.
) Compare the Intel's SIMD extension instructions and RISC-V vector instructions. c) Consider the following code where A and B are memory-based arrays and 's' a double precision FP
number also stored in memory:
for i in range (200): A[i]=A[i]*s
B[i]B[i]+ A[i] following table gives the stall cycles required between instruction producing the result and the
The
instruction using that result.
Instruction Producing Result
FP ALU operation FP ALU operation
Load Double
Load Double Integer ALU
Instruction Using Result
Another FP ALU operation Store Double
FP ALU operation
Store Double Conditional Branch
Stall cycles required
The corresponding assembly code without any scheduling is given as under:
// double precision FP load
41301

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