(a) Define segmentation

(b) There are many ways to segment a market. Briefly explain

(4) basic ways for a company to segment its market.

(c) Product is anything that can be offered to a market for attention, acquisition use or consumption that might satisfy a want or need. Briefly explain levels of product and provide an example for each level.

QUESTION 3 (a) Illustrate a product life-cycle stages chart and briefly explain the following product life-cycle stages:

i. Introduction stage

ii. Decline stage

(b) Elaborate the internal factors that influenced prices under the marketing objective of product-quality leadership.

(c) Define Market-Skimming Pricing

(d) Members of marketing channel perform many key functions. One of the functions is 'matching'. Define the function of 'matching' in distribution channel (2 marks) (e) Sales Promotion is a short-term incentive to encourage the purchase or sale of a product or service. Briefly explain TWO

(2) of the consumer promotion tools below that are commonly used by marketers to increase the sales of their product. i. Sample ii. Coupon

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of the instructions ?

Question 2

Consider an instruction pipeline with four stages (S1, S2, S3and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers. What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

Question 3

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3,..., I12is executed in this pipelined processor. Instruction I4is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is?

Question 4

Consider the 8085 instruction IN 09H stored as follows: Add the following incomplete timing diagram for the instruction : Write the contents of the boxes, A, B, C and D in hexademcimal in your answer do not draw any pictures.

(b) Write the state of both ALE andRDpins at times T1, T2, T3 and T4. (c) How do you generate the signal that tells the peripheral to put the data on the bus? Answer by completing the following statement in your answer book : By combining signals/

Question 5

In the above sequence, R0 to R8 are general purpose registers. In the instruction shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write Back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is?r