a) Determine the sizes W and L of transistors MP, MP2, MNI, MN2, MN3 and MN4 so that the overall gain is at least 70. Note that you do not need to design according to a fixed input DC level and that you can also decide the DC level of the input signal that biases M. Therefore, also decide what the DC level of the input signal will be. b) Calculate the DC operating point (Ves, VDS, ID) for each transistor. c) Calculate the voltage gain vo/vi, input and output resistances. d) What are the advantages and disadvantages of using the second stage? What would the midband gain e) Calculate the high frequency poles of the amplifier by drawing the ac equivalent circuit showing clearly the unit cells. Use the information given below: Cgs(unit)=10 frum; Cgd(unit)=0.7 fF/m, Cgs=Cgs(unit)-W-L, Cgd=Cgd(unit)W-L. f) Sketch the Bode plots of the transfer function V/V (magnitude and phase) showing all critical values. MPI se nta 20 A DD MP2 HEW MN1 VOD MN2 20 A DD 16 MN4 MN3 HWHI 1/2 1. Vcc=5 V, HnCox=250 A/V, UpCox-120 A/V2n=0.8 V, Vip= -0.9 V, An-Ap=0.05 V-1, RL-500 is given for the amplifier below. The topology will be used to achieve a gain of at least 70 (the magnitude).