a) Draw the schematic of the 3-input NOR gate, and size all the transistors such that the worst-case delay is equal to that of a unit-sized inverter WpW = 2:1. Find the logical effort gnors and parasitic delay (pNoRs) of the 3-input NOR gate. b) For the logic path from A to Out shown below, find the path logical effort (G), path branching effort (B), path electrical effort (H), path effort (F), path parasitic delay (P). What is the optimum effort per stage, fopt, for minimizing delay? What is the total path delay (D)? c) Find scaling factors (x, y, z) in order to minimize delay in the path from A to Out. d) Is it possible to match the delay of path D to Out to the minimized delay of path A to Out? If yes, find scaling factors (w) that can achieve this.