A FIFO in digital design is a memory mechanism that is comparable to the object $$queue$$ in a

computer$-$science setting. A FIFO uses a memory module to store data when written to and

ejects data when read from. It also uses a control module to organize the process. We can

abstractly realize a FIFO in hardware by keeping track of two memory addresses $($pointers$,$ if

you will$)$: a $$read address$$ and a $$write address.$$ The read address $$points$$ to the memory

location that holds the $$oldest$$ or $$least recently stored$$ data. Whenever a $$read$$ input is

asserted, the data stored in this address is output from the FIFO. On the other hand, the write

address points to a memory location that will be written to next. Whenever a $$write$$ input is

asserted, the data from the input data bus is stored in this address. The relationship between

the read and write addresses is displayed below in Figure $3$a$.$ A FIFO also always has a full and

an empty signal that signals the state of the FIFO $($whether it is full, empty, or neither$).$ A block

diagram of a FIFO can be found in Figure $3$b$.$ The inputs and outputs associated with a FIFO are

listed in Table $1$ below $($note that this is for a FIFO of width $$n$)$: