A finite state machine (FSM) is defined by the state diagram in Figure Q4. 15 "reset" is an active low, synchronous reset, " X " is an input, and " Y " is an output. (a) Is this of Moore type or of Mealy type? Why? (5) (b) If this FSM is used to detect a specific bit stream, what is the bit (3) stream? (c) Write Verilog code to implement this FSM