a) For the C-code shown in the following figure, the elements of array A take a value in the range 1 to 31 and the elements of array B take a value in the range 65 to 156. You do not have any information on how the values are arranged in the two arrays. unsigned int A[10], B[10], C[10]; unsigned int i; for(i=0; i < 10; i++) { } C[i] = A[i]+B[i]; unsigned int A[101, B[10], C[10]; unsigned int i; www ww for (i=0; i < 10; i++)+ www {+ C[i] = A[i] +B[i]; }+ If you implement this code in Vivado-HLS, all integers will be treated as 32 bit wide and the design will use area "X" on the FPGA. Write an alternate version of this piece of C-code using user-defined data-types in Vivado- HLS so that when implemented, it uses less area than "X". Explain why the new code uses less area (20 marks). N b) Name one optimization to speed up the execution of the loop. Will this optimization require the usage of more BRAM blocks? Why? (10)