A.) How many states does the Mealy machine above have?

B.) How many process blocks will you need to code this machine? (Look at the example above.)

C.) Using the VHDL from above as a guide, write the VHDL code for the Mealy machine above.

The VDH code below shows how a finite state machine is cooled in , HDL Note that is NOT a complete code. It is just a guic : to assist you in coding your FSM entity rSM is end ens ty PSM archite sture beh of FSM isS por (CLOCK,RESET....etc) beg n .his first process block listens for a change in clock and reset Thi block wil1 update your current state or reset your FSM to state process(CLOCK, RESET begin if (RESET-1 then CURRENT STATE