(a) (i) Derive the equation that describes C4 in the 4-bit carry lookahead adder in terms of the propagate, generate and carry signals of the lower significant bits (i.e. Po P1 P2 P3 Go G1 G2 G3 C0 C1 C2 C3). (ii) Work out the multi-level carry lookahead scheme for implementing a 32-bit number addition by using 4-bit carry lookahead adders. Use suitable diagrams to illustrate your answer. (iii) Determine the number of gate delays in the adder of Q 4 (a) (ii) to complete the addition of the 32-bit numbers. (b) Determine the total gate delay in an unsigned 32-bit by 32-bit multiplication hardware that uses the shift and add multiplication method with an adder as in Q4 (a) (ii) above. Assume other delay overheads are negligible. (c) Let multiplicand A = 10010101 (149) and multiplier B = 01101100 (108). Determine the four (4) bit pairing recoding Booth Algorithm (i.e. radix-4) for the multiplier B bits (i.e either 0, +1, -1,+2,-2). Hence derive the corresponding 4 partial products and illustrate your steps of the addition of each partial product to obtain the result to be 16,092.