(a) Identify which figure above corresponds to the single cycle architecture and which to the multicycle architecture.

(b) Calculate the maximum clock speed (in Hertz) allowed in the single cycle and multi-cycle architectures respectively?

(c) For a program with 40% R type, 40% I type and 20% J type instructions, which implementation is faster?

Consider the single cycle and multi-cycle implementations of the MIPS processor shown in the figures below Add result Shift left 2 Instruction [31-26] Control ALUOp ALUSro RegWrite nstruction [25-211 PC register 1 Instruction [20-16] data 1 register 2 [31-0] Registers Read data 2 Instruction [15-X Data Write memory 16 32 Instruction [15-0] Instruction 15-0] PCSource PCWrite ALUO orDOutputs ALUSrcB MemRoad MemWriteControl ALUSCA MemtoR Jump address (31-0] Instruction [25-0] Instruction [31-26] 125-21 20-16] uAddress register 1 Read register 2 data 1 ALU ALU Registers Write register data 2 Read 15-01Instruction Instruction 15-111 X Write data Ins truction [15-0] 16 ALU sign Shift left 2 The time taken by each componen in each of the wo architectures is as follous Instruction Memory Access 200 ps Register File read from stable read-register number = 100 ps ALU delay 100 ps Data Memory Access (read) 300 ps Write into registers/memory from rising edge of clock 50 ps (where ps stands for pico-seconds (1 ps-1 x 10-12 seconds)) The delays of multiplexers, control unit, shifters, and sign extension unit are assumed to be zero