A one-issue proces for uses out of order execution with a Reorder Buffer (ROB). The processor has four unified reservation stations (RSO through RS3) and eight ROB entries (ROBO through ROB7). There are two execution units. One unit can only do MUL instructions, has a 6-cycle latency, and is NOT pipelined. The other unit can do all other (non-MUL) instructions, has a 2-cycle latency, and IS pipelined. The result can be broadcast in the cycle after the execution is complete. Only one result can be broadcast in each cycle. A reservation station that has been used by an instruction is freed when the instruction is selected for execution, and another instruction can be issued into that RS during the first execution cycle of the original instruction. A ROB entry can be reused in the cycle after the one in which it was freed (you should know when that is). An instruction that is waiting for a result to be produced can begin execution in the cycle after the one in which its last missing operand is broadcast. All conflicts for resources are resolved in favor of the older instruction, i.e. the instruction that comes earlier in the program. Assume that reservation stations and the ROB are all empty at the beginning of the starting cycle (Cycle 1), and that the processor has already fetched and decoded the following instructions, so they are all waiting to be issued at the beginning of the starting cycle (Cycle 1). We have filled out the first row of the execution timing table below. You need to fill the rest of it. Instruction Issue Exe BCast Commit MUL R2, R1, 11 1 2 8 9 RO 12 MUL R2,R2 R2 13 ADDR3,RO,R4 14 ADD R4, R3, R2 15 ADD R1,R1.R1 16 ADD R3 R3 R3 A one-issue proces for uses out of order execution with a Reorder Buffer (ROB). The processor has four unified reservation stations (RSO through RS3) and eight ROB entries (ROBO through ROB7). There are two execution units. One unit can only do MUL instructions, has a 6-cycle latency, and is NOT pipelined. The other unit can do all other (non-MUL) instructions, has a 2-cycle latency, and IS pipelined. The result can be broadcast in the cycle after the execution is complete. Only one result can be broadcast in each cycle. A reservation station that has been used by an instruction is freed when the instruction is selected for execution, and another instruction can be issued into that RS during the first execution cycle of the original instruction. A ROB entry can be reused in the cycle after the one in which it was freed (you should know when that is). An instruction that is waiting for a result to be produced can begin execution in the cycle after the one in which its last missing operand is broadcast. All conflicts for resources are resolved in favor of the older instruction, i.e. the instruction that comes earlier in the program. Assume that reservation stations and the ROB are all empty at the beginning of the starting cycle (Cycle 1), and that the processor has already fetched and decoded the following instructions, so they are all waiting to be issued at the beginning of the starting cycle (Cycle 1). We have filled out the first row of the execution timing table below. You need to fill the rest of it. Instruction Issue Exe BCast Commit MUL R2, R1, 11 1 2 8 9 RO 12 MUL R2,R2 R2 13 ADDR3,RO,R4 14 ADD R4, R3, R2 15 ADD R1,R1.R1 16 ADD R3 R3 R3