Problem 618 points]: Consider a memory-system with byte-addressable memory with 32-bit physical addresses. The single-level write-back cache has 32 byte blocks and can store 2 MB of data. a) [4 points] The bus connecting the cache to memory is 4 bytes wide and has one cycle latency (i.e., it takes one cycle to transfer data and/or address over the bus). Memory is interleaved with 8 banks; each has a 20- cycle latency. Compute the miss penalty when a clean cache block is replaced, and when a dirty cache block is replaced. Draw pipeline diagrams to support your answer. b) [4 points] The cache has a hit-time of 2 cycles. For a particular program, the cache suffers a miss-rate of 10%, and 20% of cache blocks replaced are dirty. Compute the average number of cycles per memory access in this program. Show your calculations clearly.