A processor implements a fiveve-stage instruction pipeline that implements full forwarding. The following code are executed using this processor and predict always taken is employed as the branch prediction technique. LD R1, 24(R5) DADD R2, R4, R1 BEQ R2, R6, Dest DADDUI R1, R1, #1 LD R4, 4(R5) Dest: DADD R3, R2, R4 (a) Suppose the branch prediction is correct (branch is taken). Draw a dia- gram to show the pipeline stages for execution of instructions 1, 2, 3 and 6. Show the forward and stalls in the diagram if they are used. What is the speedup factor of this pipelining method when compared with not using pipelining? We assume every instruction takes 5 cycles on non-pipeline design. (b) Redraw the diagram if the prediction is wrong (branch is actually not taken). Show the execution steps from instruction 1 to 6. In this case, what is the speedup factor when compared with not using pipelining?