A proposed silicon p-channel MOSFET has a saturation current of 850 uA for VGS-V th = 0.8 V. The gate length is 20 nm, the device width is 60 nm. During initial testing, the process engineers try to verify that the oxide layer is uniformly deposited over a large area. To do this, they construct 5 um x 5 um square gates. These devices have HfO2 (&-20) oxide layers and, on average, the total capacitance between the gate and substrate contacts is 15 fF. Estimate the dopant concentration in the substrate. (15) A proposed silicon p-channel MOSFET has a saturation current of 850 uA for VGS-V th = 0.8 V. The gate length is 20 nm, the device width is 60 nm. During initial testing, the process engineers try to verify that the oxide layer is uniformly deposited over a large area. To do this, they construct 5 um x 5 um square gates. These devices have HfO2 (&-20) oxide layers and, on average, the total capacitance between the gate and substrate contacts is 15 fF. Estimate the dopant concentration in the substrate. (15)