A sign extension unit extends a twos complement number from M to N (N > M) bits by copying the most significant bit of the input into the upper bits of the output. It receives an M-bit input A and produces an N-bit output Y. A zero extension unit extends an unsigned number from M to N bits (N > M) by putting zeros in the upper bits of the output. Perform the following activities to complete the task: 1. Add the template file extend.sv in the project created in Task1 using Project -> Add/Remove files in project. Browse the extend.sv file and add it into the project. Set this file as top-level entity. 2. Complete the extend.sv file using if-else statement and bit swizzling.3. Perform Analysis & Synthesis using Processing -> Start -> Analysis & Synthesis. 4. The compilation should take place without errors and warnings. If you find any error or warnings, then fix it. 5. Create a University Program VWF using File -> New -> University Program VWF. Configure the file with the following specification: a. Insert all signal nodes/buses using Edit -> Insert -> Insert Node or Bus -> Node Finder -> List. Then add all the nodes in Nodes found to Selected Nodes by pressing the >> button. b. Set the simulation end time to 10ns using Edit -> Set End Time. c. Set the grid size to 1ns using Edit -> Grid Size. d. Use the Random values button to configure input signals to cycle through random logic bus values throughout the simulation. e. Start functional simulation using Simulation -> Run Functional Simulation and verify whether outputs are getting the correct values. Deliverables 1. [4 points] Code screenshot of extend.sv file and upload the file separately. 2. [1 points] Screenshot of successful compilation of extend module. 3. [1 points] Screenshot of simulation result for the module. 4. [1 points] Screenshot of RTL Viewer of the module.

Answer: diagram and code

Consider the following diagram:

The above diagram shows the Symbol for Sign extension unit. Now consider the following diagram:

The above given diagram shows the Function for fundamental hardware

The following HDL module is used for the design of the above diagram.

HDL module

Verilog

module sign_ext_4_8(input [3:0] s, //four bit input s taken

//Eight bit output x

output [7:0] x);

//4 bit vector is assigned to x

assign x = { {4{s[3]}}, s};

//end of the module

endmodule

VHDL

library IEEE;

//In order to use any of the declaration in STD_LOGIC_1164 package user have to use IEEE and use clause.

use IEEE.STD_LOGIC_1164.all;

entity sign_ext_4_8 is

--Taking s as 4-bit input vector

port(s: in STD_LOGIC_VECTOR(3 downto 0);

--std_logic same as bit, multiple inputs of the same

--type can be defined on the same line separated by commas

x: out STD_LOGIC_VECTOR(7 downto 0));

--end of the entity

end;

architecture synth of sign_ext_4_8 is

--Starts loop here.

begin

-- assign it into x

x

end;