A superscalar processor, shown below, uses in-order-issue-in-order-completion" policy. Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Point Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. Show the execution sequence of the program. Also calculate the run time if the CPU uses 2GHz clock. Instructions Comment ADDR3, R1, R2 FPU LOAD R6, [R3] AND R1, R6, R1 ADD R1, R6, RO FPU FPU SUB R2, R1, R6 AND R4, R3, 15 LOAD R6, [R4] SUB RS, R3, R4 ADD RO, R1, R6 SHL R7, RO, 8 System Integer ALU Write-back Unit-1 Decode Unit-1 Fetch Unit-1 Floating Point Unit Write-back Unit-2 Decode Unit-2 Fetch Unit-2 Integer ALU A superscalar processor, shown below, uses in-order-issue-in-order-completion" policy. Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Point Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. Show the execution sequence of the program. Also calculate the run time if the CPU uses 2GHz clock. Instructions Comment ADDR3, R1, R2 FPU LOAD R6, [R3] AND R1, R6, R1 ADD R1, R6, RO FPU FPU SUB R2, R1, R6 AND R4, R3, 15 LOAD R6, [R4] SUB RS, R3, R4 ADD RO, R1, R6 SHL R7, RO, 8 System Integer ALU Write-back Unit-1 Decode Unit-1 Fetch Unit-1 Floating Point Unit Write-back Unit-2 Decode Unit-2 Fetch Unit-2 Integer ALU