A synchronous Moore FSM has a single input, x_in , and a single output y_out . The machine is to monitor the input and remain in its initial state until a second sample of x_in is detected to be 1. Upon detecting the second assertion of x_iny_out is to asserted and remain asserted until a fourth assertion of x_in is detected. When the fourth assertion of x_in is detected the machine is to return to its initial state and resume monitoring of x_in .

(a) Draw the state diagram of the machine.

(b) Write and verify a Verilog model of the machine.